Normal transport

ACTIVE (14) + status bit 7 set. Control-byte layer for menus, setup, bulk data, and the phase barriers that gate gameplay.

Control bytes F0–F7

Receiver subtracts F0, rejects > 7. Low 3 bits are flags:

Bit	+val	Meaning
0	1	phase-ready barrier (level, not a per-packet ack)
1	2	event toggle — flips peer state, reloads 60-tick timer
2	4	payload follows (count byte + ring bytes)

Base F0 normally, F1 during a barrier:

Value	Meaning
F0	idle
F2 / F4 / F6	+event / +payload / +both
F1 F3 F5 F7	same, barrier base

Phase barrier

Bit 0 is a symmetric level barrier. Local ready bit snapshots to 0x5651, received to 0x5652; transition waits until both == 1. Base switches to F1 during the barrier. This is how the game crosses into F8 gameplay.

Bulk payload (ring buffer)

Bit 2 set → <control|4> <count:7> <count bytes>. TX ring at 0x566d, RX ring at 0x56ad, both 64 bytes (& 0x3f). BIOS COMCREATEBUFDATA/COMGETBUFDATA split at the ring boundary.

• F9 — bulk ACK; sender clears its in-flight TX count on receipt.
• FA — accepted mid-transfer but doesn't clear it; no producer in the ROM (receive-only/reserved).

RAM

Address	Role
0x5653	base control (F0/F1)
0x5651 / 0x5652	local / received phase-ready
0x5655	peer event (bit 0), pending local event (bit 7)
0x5656	60-tick watchdog
0x5659 / 0x565b	TX count / ring index
0x565d / 0x565e	RX count / ring index

Event flag set → 0x5656 counts down; at 0 → timeout (0x564f = FF). Full map: RAM variables.